CAS Latency and Clock Frequency
CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400B DDR400A -5 -5A 133 133 166 200 200 200
* Double data rate architecture:.
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double .
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